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[Embeded-SCM Develop] Flash_FPAG_JTAG

Description: FPGA或者CPLD通过JTAG接口对FLASH进行读写的资料。非常有用-Programming Flash Memory from FPAGs and CPLDs Using the JTAG Port. Very useful
Platform: | Size: 305152 | Author: superstar | Hits:

[Embeded-SCM Develop] NAND_FLASH_simulation_model

Description:
Platform: | Size: 849920 | Author: andrew zhang | Hits:

[OS Develop] RT_8051_memory

Description: 8051 RT Memory Verilog-8051 Memory
Platform: | Size: 4096 | Author: feisikair | Hits:

[VHDL-FPGA-Verilog] fft_1024_hdl

Description: 一个 1024 点 FFT ， 基 4 蝶形运算架构， 5级流水，乒乓内存，有测试环境。-A 1024-point FFT, Radix-4 butterfly structure operation, five water, ping-pong memory, a test environment.
Platform: | Size: 18432 | Author: wei | Hits:

[Communication-Mobile] CAM

Description: CAM cord of VHDL. CAM(content addressable memory)- CAM cord of VHDL
Platform: | Size: 1024 | Author: li | Hits:

[VHDL-FPGA-Verilog] memory_game.asm

Description: example for memory game in vhdl
Platform: | Size: 2048 | Author: ido | Hits:

[VHDL-FPGA-Verilog] flash

Description: fpga的FLASH读写VERILOG代码。希望对大家有用-the verilog code of fpga read/write flash
Platform: | Size: 1024 | Author: Denny | Hits:

[Other] uc_interface

Description: This file provides an 8051 external data memory bus interface for CoolRunner CPLDs. This file contains the state machine to interface on the 8051 bus as well as the address registers, the address decode logic, and example control registers, status registers, data input registers, and data output registers. Interrupt logic is also included. Note that this code should be modified to meet the requirements of the system. -This file provides an 8051 external data memory bus interface for CoolRunner CPLDs. This file contains the state machine to interface on the 8051 bus as well as the address registers, the address decode logic, and example control registers, status registers, data input registers, and data output registers. Interrupt logic is also included. Note that this code should be modified to meet the requirements of the system.
Platform: | Size: 4096 | Author: alex | Hits:

[SCM] 1

Description: VGA01目录下有TTOP.BIN，下载后有如下效果： 插上显示屏： 屏幕显示两层图片，下层是静态的两个字，我的名字。 上层是一个128X64的256色图片， 插上键盘： 按键盘大键盘区的1－9,板子上的7段会有显示数字，按<-删除键删除一个数字。 visualC目录下是一个小程序，将BMP转换成rom.mif ROM存储器初始化文件。-VGA01 directory under TTOP.BIN, download the following effect: plug in the display: two-tier display picture, the lower is the word static, my name. 128X64 upper is a 256 color photos, plug in the keyboard: the keyboard great keyboard by the 1-9 zone, the board will show the number of paragraph 7, according to <- Delete key to delete a number. visualC directory is a small program to convert BMP memory initialization file rom.mif ROM.
Platform: | Size: 1695744 | Author: jinbang | Hits:

[Technology Management] dds9851

Description: 本文主要介绍的是采用直接数字频率合成的短波信号发生器，它主要以微电脑控制部分、直接数字频率合成（DDS）部分、数字锁相环频率合成部分、背光液晶显示部分、功率放大部分等组成。该软件系统采用菜单形式进行操作，操作方便明了，增加了很多功能。它通过启动DDS后，把内存缓存区的数据送到DDS后输出相应的频率，并把数据转换为BCD码，送到液晶显示器进行显示。该系统输出稳定度、精度极高，适用于当代的尖端的通信系统和精密的高精度仪器。-This paper describes the use of direct digital frequency synthesis of short-wave signal generator, which is part of a micro-computer control, Direct Digital Synthesis (DDS) of the digital part of PLL frequency synthesizer, backlit liquid crystal display of the power amplifier, etc. composition. The menu system uses the form of software to operate, easy to operate and clear, increase in the number of features. DDS through start after the memory cache after the data to the DDS output corresponding frequency, and the data is converted to BCD code to the LCD display. The output of the system stability, high precision for cutting-edge contemporary and sophisticated communication systems high-precision instruments
Platform: | Size: 466944 | Author: xiang | Hits:

[VHDL-FPGA-Verilog] micro

Description: 16 cpu design VHDL source code, including alu, clock, memory and other parts of the design
Platform: | Size: 30720 | Author: mojo | Hits:

[Windows Develop] fifo_design

Description: 异步fifo的设计，能够很好的的完成，数据的缓冲，内部有ram存储器-The design of asynchronous fifo， Asynchronous fifo design, can be a good completion of the data buffer, internal ram memory
Platform: | Size: 2048 | Author: 孟霑 | Hits:

[Other Embeded program] zdshj

Description: 自动售货机控制系统设计 要求： 设计制作一个自动售货机控制系统。 该系统能完成货物信息存储，进程控制，硬币处理，余额计算，显示等功能。 该系统可以管理四种货物，每种的数量和单价在初始化时输入，在存储器中存储。用户可以用硬币进行购物，按键进行选择。 系统根据用户输入的货币，判断钱币是否够，钱币足够则根据顾客的要求自动售货，钱币不够则给出提示并退出。 系统自动的计算出应找钱币余额、库存数量并显示。 -Vending machine control system design requirements: Design a vending machine control system. The system can complete cargo information storage, process control, coin handling, balance calculation, display and other functions. The system can manage four kinds of goods, the quantity and unit price of each in the initialization input, stored in memory. Users can use coins shopping button to choose. The monetary system based on user input to determine whether enough money, coins, according to customer requirements is sufficient Vending, coins were not given prompt and exit. The system automatically calculate the balance should be looking for coins, inventory number and displayed.
Platform: | Size: 67584 | Author: dws | Hits:

[VHDL-FPGA-Verilog] ram

Description: 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个RAM存储器。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a RAM memory.
Platform: | Size: 198656 | Author: Daisy | Hits:

[VHDL-FPGA-Verilog] rom

Description: 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个ROM存储器。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a ROM memory.
Platform: | Size: 179200 | Author: Daisy | Hits:

[ARM-PowerPC-ColdFire-MIPS] TEST_NANDFLASH

Description: 典型NANDFLASH功能模块描述，扩展外部存储器时可有效运用-Typical NANDFLASH functional modules described, extending the effective use of external memory when
Platform: | Size: 2048 | Author: zheshu | Hits:

[VHDL-FPGA-Verilog] sdram_ver_134

Description: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is based Xilinx FPGA Playform.
Platform: | Size: 108544 | Author: peace | Hits:

[VHDL-FPGA-Verilog] sdram_vhd_134

Description: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is Verilog. This code is based Xilinx FPGA Playform.
Platform: | Size: 488448 | Author: peace | Hits:

[VHDL-FPGA-Verilog] c_xapp454

Description: 这是xilinx应用指南xapp454的中文版本。本应用指南说明与 Micron DDR2 SDRAM 器件连接时，Spartan™ -3 器件中 DDR2 SDRAM 存储器接口的实现。本文档先简单介绍了 DDR2 SDRAM 器件的特性，然后对 DDR2 SDRAM 存储器接口的实现进行了详细说明。-This is the xilinx application note xapp454 the Chinese version. This application note and the Micron DDR2 SDRAM device is connected, Spartan ™ -3 devices DDR2 SDRAM memory interface implementation. This document briefly describes the DDR2 SDRAM device features, and then the realization of DDR2 SDRAM memory interface is described in detail.
Platform: | Size: 217088 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] 4by4

Description: 4输入，4输出，clos网络所用，有利于连接处理器和处理器，处理器和存储器传输数据。-4 inputs, 4 outputs, clos network use is conducive to connecting the processor and processor, processor and memory to transfer data.
Platform: | Size: 1024 | Author: davidsun | Hits:
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